1. Field of the Invention
The invention relates to a method for outputting data and a circuit configuration with a driver circuit for outputting the data. More specifically, two input signals are amplified in parallel for generating the output data.
Integrated circuits such as processors and semiconductor memories have output drivers (off-chip drivers (OCD)) in order to amplify and output signals that are stored in memory cells of the memory. The output drivers used have a high driver capability in order to be able to generate an output signal that can be identified unambiguously even in the case of a high load. The high driver capability and the associated large temporal gradient of the current change at the output of the output drivers have the disadvantage that high interference voltages are generated in the event of a change in the amplitude of the output signal. When there is a multiplicity of output drivers, a large current flow is generated, with the result that the internal voltage supply is subjected to severe fluctuations. In particular, there is the risk of the ground potential being raised as far as the region of the switching threshold of transistors. This can result in erroneous behavior and the loss of switching states.
U.S. Pat. No. 5,963,047 discloses a CMOS output buffer circuit that suppresses noise signals on adjacent input pins. Each output buffer has a weak and a strong pull-down transistor. The strong pull-down transistor is switched off during a switching time in which reflections occur. Furthermore, a turn-off device is provided, which inhibits the strong pull-down transistors of adjacent input pins when reflections of an output buffer occur.
Published, European Patent Application EP 0 586 207 A1 discloses a circuit configuration for an output driver which has a plurality of output lines. On the various output lines, the signals are changed over in a manner dependent on the instant of the change from a low state to a high state or from a high state to a low state with gradients of different magnitudes. In this case, only a single gradient is used for a respective output signal of an output line. What is achieved in this way is that all the outputs are at the changed-over high or low state up to a predetermined instant.
U.S. Pat. No. 5,568,081 discloses a control device for an output buffer that can adjust the temporal gradient of an output signal. The temporal gradient of the output signal is varied in a manner dependent on the temporal gradient of the current of the output signal. The setting of the temporal gradient of the output signal is chosen to be small in the case of a large temporal gradient of the current and large in the case of a small temporal gradient of the current.
It is accordingly an object of the invention to provide a method for outputting data and a circuit configuration with a driver circuit that overcomes the above-mentioned disadvantages of the prior art methods and devices of this general type, with which interference voltages are reduced.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for the parallel amplification of two input signals including a first input signal and a second input signal, a first amplified output signal being formed from the first input signal and a second amplified output signal being formed from the second input signal. The method includes performing the following steps in an event of a change in amplitudes of the two input signals in a predetermined time period: changing the first amplified output signal with a first temporal gradient during a first time period; changing the first amplified output signal with a second temporal gradient during a second time period, the first temporal gradient being larger than the second temporal gradient; changing the second amplified output signal with a third temporal gradient during a third time period; and changing the second amplified output signal with a fourth temporal gradient during a fourth time period, the fourth temporal gradient being larger than the third temporal gradient.
One advantage of the invention is that, in the event of a virtually simultaneous change in the input signal, output signals are changed with different temporal gradients in a first and second and, respectively, third and fourth time period. In this way, the gradients of the output signals can be coordinated with one another, with the result that only a small interference voltage is output.
Preferably, the change of the first and second output signals is begun simultaneously. An exceptional reduction of the interference voltage that is output is achieved by virtue of the fact that the temporal gradients of the two output signals do not simultaneously have a maximum gradient. Therefore, overall, a smaller interference voltage is output by the two output signals.
In a preferred embodiment, the first and second and, respectively, the third and fourth time periods and the corresponding temporal gradients of the first and second output signals are chosen such that the first and second output signals simultaneously reach a maximum high level and a minimum low level, respectively.
The method is preferably used for reading out information stored in memory cells of a memory, in particular of a semiconductor memory.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration. The circuit contains two driver circuits, including a first driver circuit and a second driver circuit, for a parallel read-out of signals. Each of the two driver circuits has an input for receiving one of two input signals and an output. An adapting circuit is connected to the input of each of the two driver circuits, and in that, in an event of a change of amplitudes of the two input signals in a predetermined time period, the adapting circuit changes a first output signal with a first temporal gradient in a first time period and then changes the first output signal with a second temporal gradient being smaller than the first temporal gradient in a second time period. The adapting circuit also changes a second output signal with a third temporal gradient in a third time period and then changes the second output signal with a fourth temporal gradient in a fourth time period, the fourth temporal gradient being larger than the third temporal gradient.
A preferred embodiment prescribes two driver circuits for the parallel reading out of signals, at least one driver circuit being connected to an adapting circuit. The adapting circuit is connected to the inputs of the first and second driver circuits. In the event of a simultaneous change in the input signal to a new potential state, the adapting circuit changes an output signal with a first temporal gradient in a first time period and then with a second temporal gradient in a second time period.
In a preferred embodiment, a second adapting circuit is only connected to the second data output, with the result that the adapting circuit changes the second output signal with a third temporal gradient in a third time period and then changes it with a fourth temporal gradient in a fourth time period.
Preferably, the adapting circuit has a first and a second path, via which a gate terminal of the output transistor can be connected to a switching potential. At least one switch is disposed in each path, the switch being connected to the first and second signal inputs via a delay circuit. On account of the delay circuit, the two switches are switched in a temporally staggered manner. In this way, the temporal gradient of the gate voltage at the gate terminal is prescribed such that it has different magnitudes in different time periods.
In a simple embodiment, a gate is disposed as the delay circuit. The switch is preferably a field-effect transistor.
A preferred embodiment of the first and second driver circuits consists in the configuration of a first and third and, respectively, a second and fourth output transistor. The first and third and, respectively, the second and fourth output transistors are preferably PMOS and, respectively, as NMOS field-effect transistors. The first and third and, respectively, the second and fourth output transistors are connected in series via a respective connecting line, a first and second signal output, respectively, being connected to the connecting line.
In accordance with an added feature of the invention, the first driver circuit has a first output circuit and the second driver circuit has a second output circuit.
In accordance with another feature of the invention, the first output circuit includes a connecting line, a first output transistor having a gate terminal, and a second output transistor having a gate terminal. The first and second output transistors are connected in series through the connecting line. The connecting line is connected to the output of the first driver circuit, and the gate terminal of the first and/or second output transistors is connected to the adapting circuit.
In accordance with an additional feature of the invention, the second output circuit has a connecting line, a first output transistor with a gate terminal, and a second output transistor with a gate terminal. The first and second output transistors are connected in series through the connecting line. The connecting line is connected to the output of the second driver circuit. The gate terminal of the first and/or second output transistors is connected to the adapting circuit.
In accordance with a further feature of the invention, the first output transistor is a PMOS transistor having an input and the second output transistor is an NMOS field-effect transistor, the input of the PMOS transistor is to be connected to a high voltage potential and the input of the NMOS field-effect transistor is to be connected to a low voltage potential.
In accordance with a further added feature of the invention, the adapting circuit connects the gate terminal of the first output transistor and/or the second output transistor to a predetermined potential via two paths. Two switches are provided with one of the switches disposed in each of the two paths. The two switches are coupled to the input of the first driver circuit through a delay circuit. The delay circuit is connected to the two switches and opens or closes the two switches in an event of a change of a state of the two input signals in the predetermined time period, including in an event of a simultaneous change, at different instants.]
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for outputting data and a circuit configuration with a driver circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.